Systemc


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SystemCrafter SC  v.3.0

SystemCrafter SC is a SystemC synthesis tool for Xilinx FPGAs. SystemCrafter SC generates RTL VHDL or Verilog for downstream synthesis to Xilinx FPGAs, and closes the verification gap by writing a structural SystemC output for simulation.

Active-HDL  v.8. 3. 2026

Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator.





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OMNeT++  v.3 3

OMNeT is an extensible, modular, component-based C simulation library and framework, primarily for building network simulators.

CapsimTMK  v.1.0

Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.

HDLObf  v.1.0

HDLObf is intended to be a HDL Obfuscator and identifier name change utility.

Scansion  v.1.3

Scansion is a native OSX application for viewing analog and digital simulation waveforms from VCD files as well as transaction level modeling (TLM) traces.

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